MC68HC711E9CFNE2 Freescale Semiconductor, MC68HC711E9CFNE2 Datasheet - Page 173

• Manufacturer Part Number: MC68HC711E9CFNE2
• Description: IC MCU 8BIT 512RAM 52-PLC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711E9CFNE2

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: OTP
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Processor Series: HC711E
• Core: HC11
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 2 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.8.1 Serial Peripheral Control Register
M68HC11E Family — Rev. 3.2
MOTOROLA
Address:
SPIE — Serial Peripheral Interrupt Enable Bit
SPE — Serial Peripheral System Enable Bit
DWOM — Port D Wired-OR Mode Bit
MSTR — Master Mode Select Bit
Reset:
Read:
Write:
Set the SPE bit to 1 to request a hardware interrupt sequence each
time the SPIF or MODF status flag is set. SPI interrupts are inhibited
if this bit is clear or if the I bit in the condition code register is 1.
When the SPE bit is set, the port D bit 2, 3, 4, and 5 pins are dedicated
to the SPI function. If the SPI is in the master mode and DDRD bit 5
is set, then the port D bit 5 pin becomes a general-purpose output
instead of the SS input.
DWOM affects all port D pins.
It is customary to have an external pullup resistor on lines that are
driven by open-drain devices.
0 = SPI system interrupts disabled
1 = SPI system interrupts enabled
0 = SPI system disabled
1 = SPI system enabled
0 = Normal CMOS outputs
1 = Open-drain outputs
0 = Slave mode
1 = Master mode
Figure 8-3. Serial Peripheral Control Register (SPCR)
U = Unaffected
$1028
SPIE
Bit 7
0
Serial Peripheral Interface (SPI)
SPE
6
0
DWOM
5
0
MSTR
4
0
CPOL
3
0
Serial Peripheral Interface (SPI)
CPHA
2
1
SPR1
U
1
Technical Data
SPI Registers
SPR0
Bit 0
U
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