MC68HC711E9CFNE2 Freescale Semiconductor, MC68HC711E9CFNE2 Datasheet - Page 52

• Manufacturer Part Number: MC68HC711E9CFNE2
• Description: IC MCU 8BIT 512RAM 52-PLC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711E9CFNE2

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: OTP
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Processor Series: HC711E
• Core: HC11
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 2 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Central Processor Unit (CPU)
3.3.6.4 Negative (N)
3.3.6.5 Interrupt Mask (I)
3.3.6.6 Half Carry (H)
3.3.6.7 X Interrupt Mask (X)
Technical Data
52
The N bit is set if the result of an arithmetic, logic, or data manipulation
operation is negative (MSB = 1). Otherwise, the N bit is cleared. A result
is said to be negative if its most significant bit (MSB) is a 1. A quick way
to test whether the contents of a memory location has the MSB set is to
load it into an accumulator and then check the status of the N bit.
The interrupt request (IRQ) mask (I bit) is a global mask that disables all
maskable interrupt sources. While the I bit is set, interrupts can become
pending, but the operation of the CPU continues uninterrupted until the
I bit is cleared. After any reset, the I bit is set by default and can only be
cleared by a software instruction. When an interrupt is recognized, the I
bit is set after the registers are stacked, but before the interrupt vector is
fetched. After the interrupt has been serviced, a return-from-interrupt
instruction is normally executed, restoring the registers to the values that
were present before the interrupt occurred. Normally, the I bit is 0 after
a return from interrupt is executed. Although the I bit can be cleared
within an interrupt service routine, "nesting" interrupts in this way should
only be done when there is a clear understanding of latency and of the
arbitration mechanism. Refer to
The H bit is set when a carry occurs between bits 3 and 4 of the
arithmetic logic unit during an ADD, ABA, or ADC instruction. Otherwise,
the H bit is cleared. Half carry is used during BCD operations.
The XIRQ mask (X) bit disables interrupts from the XIRQ pin. After any
reset, X is set by default and must be cleared by a software instruction.
When an XIRQ interrupt is recognized, the X and I bits are set after the
registers are stacked, but before the interrupt vector is fetched. After the
interrupt has been serviced, an RTI instruction is normally executed,
causing the registers to be restored to the values that were present
before the interrupt occurred. The X interrupt mask bit is set only by
Central Processor Unit (CPU)
Section 5. Resets and
M68HC11E Family — Rev. 3.2
Interrupts.
MOTOROLA