MC68HC711E9CFNE2 Freescale Semiconductor, MC68HC711E9CFNE2 Datasheet - Page 73

• Manufacturer Part Number: MC68HC711E9CFNE2
• Description: IC MCU 8BIT 512RAM 52-PLC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711E9CFNE2

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: OTP
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Processor Series: HC711E
• Core: HC11
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 2 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

M68HC11E Family — Rev. 3.2
MOTOROLA
$100A
$100B
$1003
$1004
$1005
$1006
$1007
$1008
$1009
Addr.
Port C Data Direction Register
Port D Data Direction Register
Port C Latched Register
Timer Compare Force
Port C Data Register
Port B Data Register
Port D Data Register
Port E Data Register
Figure 4-7. Register and Control Bit Assignments (Sheet 2 of 8)
Register (CFORC)
Register Name
See page 136.
See page 136.
See page 137.
See page 137.
See page 138.
See page 138.
See page 139.
See page 190.
(PORTCL)
Reserved
(PORTC)
(PORTD)
(PORTB)
(PORTE)
(DDRC)
(DDRD)
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Operating Modes and On-Chip Memory
I = Indeterminate after reset
DDRC7 DDRC6
FOC1
PCL7
Bit 7
PC7
PB7
PE7
R
U
0
0
0
0
0
= Unimplemented
FOC2
PCL6
PC6
PB6
PE6
R
U
6
0
0
0
0
0
DDRC5
DDRD5
FOC3
PCL5
PC5
PB5
PD5
PE5
R
5
0
0
0
0
I
Indeterminate after reset
Indeterminate after reset
Indeterminate after reset
DDRC4
DDRD4
FOC4
PCL4
PC4
PB4
PD4
PE4
R
R
4
0
0
0
0
I
Operating Modes and On-Chip Memory
= Reserved
DDRC3
DDRD3
FOC5
PCL3
PC3
PD3
PB3
PE3
R
3
0
0
0
0
I
DDRC2
DDRD2
PCL2
U = Unaffected
PC2
PB2
PD2
PE2
R
2
0
0
0
0
I
DDRC1 DDRC0
DDRD1 DDRD0
PCL1
PC1
PB1
PD1
PE1
Technical Data
R
1
0
0
0
0
I
Memory Map
PCL0
Bit 0
PC0
PD0
PB0
PE0
R
0
0
0
0
I
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