DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 1007

Manufacturer Part Number

DS72030W200FPV

MPU, 32BIT, SH7203, ROMLESS, 240QFP

Manufacturer

Renesas Electronics America

Program Memory Size

Digital Ic Case Style

Supply Voltage Range

1.1V To 1.3V

Operating Temperature Range

-20Â°C To +85Â°C

Rohs Compliant

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Bit 15 — Enable Timer: When this bit is set, the timer TCNTR is running. When this bit is

cleared, TCNTR and CCR are cleared.

Bit 14 — TimeStamp value: Specifies if the Timestamp for transmission and reception in

Mailboxes 15 to 1 must contain the Cycle Time (CYCTR) or the concatenation of CCR[5:0] +

CYCTR[15:6]. This feature is very useful for time triggered transmission to monitor Rx_Trigger.

This register does not affect the TimeStamp for Mailboxes 30 and 31.

Bit 13 — Cancellation by TCMR2: The messages in the transmission queue are cancelled by

setting TXCR, when both this bit and bit12 are set and compare match occurs when RCAN-TL1 is

not in the Halt status, causing the setting of all TXCR bits with the corresponding TXPR bits set.

Bit 12 — TCMR2 compare match enable: When this bit is set, IRR11 is set by TCMR2

compare match.

Bit15: TTCR0 15

Bit14: TTCR0 14

Bit13: TTCR0 13

Bit12 TTCR0 12

Timer and CCR are cleared and disabled (initial value)

Timer is running

CYCTR[15:0] is used for the TimeStamp in Mailboxes 15 to 1 (initial value)

CCR[5:0] + CYCTR[15:6] is used for the TimeStamp in Mailboxes 15 to 1

Cancellation by TCMR2 compare match is disabled (initial value)

Cancellation by TCMR2 compare match is enabled

IRR11 isn't set by TCMR2 compare match (initial value)

IRR11 is set by TCMR2 compare match

Section 19 Controller Area Network (RCAN-TL1)

Rev. 3.00 Sep. 28, 2009 Page 975 of 1650

REJ09B0313-0300