DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 462
DS72030W200FPV
Manufacturer Part Number
DS72030W200FPV
Description
MPU, 32BIT, SH7203, ROMLESS, 240QFP
Manufacturer
Renesas Electronics America
Series
SH7200r
Datasheet
1.R5S72030W200FP.pdf
(1686 pages)
Specifications of DS72030W200FPV
Core Size
32bit
Program Memory Size
32KB
Cpu Speed
200MHz
Digital Ic Case Style
QFP
No. Of Pins
240
Supply Voltage Range
1.1V To 1.3V
Operating Temperature Range
-20°C To +85°C
Svhc
No SVHC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Section 10 Direct Memory Access Controller (DMAC)
Figure 10.4 shows how the priority order changes when channel 0 and channel 3 transfers are
requested simultaneously and a channel 1 transfer is requested during the channel 0 transfer. The
DMAC operates as follows:
1. Transfer requests are generated simultaneously to channels 0 and 3.
2. Channel 0 has a higher priority, so the channel 0 transfer begins first (channel 3 waits for
3. A channel 1 transfer request occurs during the channel 0 transfer (channels 1 and 3 are both
4. When the channel 0 transfer ends, channel 0 is given the lowest priority among the round-robin
5. At this point, channel 1 has a higher priority than channel 3, so the channel 1 transfer begins
6. When the channel 1 transfer ends, channel 1 is given the lowest priority among the round-robin
7. The channel 3 transfer begins.
8. When the channel 3 transfer ends, channels 3 and 2 are lowered in priority so that channel 3 is
Rev. 3.00 Sep. 28, 2009 Page 430 of 1650
REJ09B0313-0300
transfer).
waiting)
channels.
(channel 3 waits for transfer).
channels.
given the lowest priority among the round-robin channels.
Transfer request
(1) Channels 0 and 3
(3) Channel 1
Figure 10.4 Changes in Channel Priority in Round-Robin Mode
Waiting channel(s)
1, 3
3
3
None
(2) Channel 0 transfer start
(4) Channel 0 transfer ends
(5) Channel 1 transfer starts
(6) Channel 1 transfer ends
(7) Channel 3 transfer starts
(8) Channel 3 transfer ends
DMAC operation
Priority order
changes
Priority order
changes
Priority order
changes
Channel priority
0 > 1 > 2 > 3 > 4 > 5 > 6 > 7
1 > 2 > 3 > 0 > 4 > 5 > 6 > 7
2 > 3 > 0 > 1 > 4 > 5 > 6 > 7
0 > 1 > 2 > 3 > 4 > 5 > 6 > 7
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