DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 1212

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DS72030W200FPV

Manufacturer Part Number
DS72030W200FPV
Description
MPU, 32BIT, SH7203, ROMLESS, 240QFP
Manufacturer
Renesas Electronics America
Series
SH7200r
Datasheet

Specifications of DS72030W200FPV

Core Size
32bit
Program Memory Size
32KB
Cpu Speed
200MHz
Digital Ic Case Style
QFP
No. Of Pins
240
Supply Voltage Range
1.1V To 1.3V
Operating Temperature Range
-20°C To +85°C
Svhc
No SVHC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Section 23 USB 2.0 Host/Function Module (USB)
Table 23.13 Conditions for Clearing the BRDY Bit
Rev. 3.00 Sep. 28, 2009 Page 1180 of 1650
REJ09B0313-0300
BRDYM
0
1
(1) Zero-length packet reception or data packet reception when BFRE = 0
(2) Data packet reception when BFRE = 1 (short packet reception/transaction counter completion)
(3) Packet transmission
USB bus
USB bus
BRDY
interrupt
USB bus
BRDY
interrupt
BRDY
interrupt
(short packet reception/transaction counter completion/buffer full)
Figure 23.3 Timing at which a BRDY Interrupt Is Generated
Conditions for Clearing the BRDY Bit
When software clears all of the bits in BRDYSTS, this module clears the BRDY
bit in INSTS0.
When the BTST bits for all pipes are cleared to 0, this module clears the BRDY
bit in INTSTS0.
Token packet
Token packet
Buffer write
Token packet
Zero-length packet/
(transaction count)
Short data packet/
(transaction count)
short data packet/
data packet (full)
A BRDY interrupt is generated
because reading from the buffer
is enabled.
data packet
A BRDY interrupt is generated
because the transfer has ended
A BRDY interrupt is generated
because writing to the buffer is enabled.
Data packet
ACK handshake
ACK handshake
ACK handshake
Buffer read

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