DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 1449

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DS72030W200FPV

Manufacturer Part Number
DS72030W200FPV
Description
MPU, 32BIT, SH7203, ROMLESS, 240QFP
Manufacturer
Renesas Electronics America
Series
SH7200r
Datasheet

Specifications of DS72030W200FPV

Core Size
32bit
Program Memory Size
32KB
Cpu Speed
200MHz
Digital Ic Case Style
QFP
No. Of Pins
240
Supply Voltage Range
1.1V To 1.3V
Operating Temperature Range
-20°C To +85°C
Svhc
No SVHC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
28.2.11 Deep Standby Control Register 2 (DSCTR2)
DSCTR2 is an 8-bit readable/writable register that controls the state of the external bus control
pins and specifies the startup method when deep standby mode is canceled. Only byte access is
valid.
Note: When writing to this register, see section 28.4, Usage Notes.
Bit
7
6
5 to 0
Bit Name
CS0KEEPE 0
RAMBOOT
Initial value:
Initial
Value
0
All 0
R/W:
Bit:
KEEPE
R/W
CS0
7
0
R/W
R/W
R/W
R
BOOT
R/W
RAM
6
0
Description
Retention of External Bus Control Pin State
0: The state of the external bus control pins is not
1: The state of the external bus control pins is
Selection of Startup Method After Return from Deep
Standby Mode
If deep standby mode is canceled by the MRES, NMI,
or IRQ bit, the program counter (PC) and the stack
pointer (SP) are read from the following addresses,
respectively, in the power-on reset exception
handling.
0: Addresses H'00000000 and H'00000004
1: Addresses H'FFFF8000 and H'FFFF8004
Reserved
These bits are always read as 0. The write value
should always be 0.
R
5
0
-
retained when deep standby mode is canceled.
retained when deep standby mode is canceled.
R
4
0
-
R
3
0
-
Rev. 3.00 Sep. 28, 2009 Page 1417 of 1650
R
2
0
-
R
1
0
-
Section 28 Power-Down Modes
R
0
0
-
REJ09B0313-0300

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