DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 831
DS72030W200FPV
Manufacturer Part Number
DS72030W200FPV
Description
MPU, 32BIT, SH7203, ROMLESS, 240QFP
Manufacturer
Renesas Electronics America
Series
SH7200r
Datasheet
1.R5S72030W200FP.pdf
(1686 pages)
Specifications of DS72030W200FPV
Core Size
32bit
Program Memory Size
32KB
Cpu Speed
200MHz
Digital Ic Case Style
QFP
No. Of Pins
240
Supply Voltage Range
1.1V To 1.3V
Operating Temperature Range
-20°C To +85°C
Svhc
No SVHC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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16.3.4
SSER enables transmission/reception and interrupt requests.
Bit
2 to 0
Bit
7
6
5, 4
3
Bit Name
CKS[2:0]
Bit Name
TE
RE
⎯
TEIE
SS Enable Register (SSER)
Initial
Value
000
Initial value:
Initial
Value
0
0
All 0
0
R/W:
Bit:
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
TE
7
0
R/W
RE
6
0
Description
Transfer Clock Rate Select
Select the transfer clock rate (prescaler division rate)
when an internal clock is selected.
000: Reserved
001: Pφ/4
010: Pφ/8
011: Pφ/16
100: Pφ/32
101: Pφ/64
110: Pφ/128
111: Pφ/256
Description
Transmit Enable
When this bit is set to 1, transmission is enabled.
Receive Enable
When this bit is set to 1, reception is enabled.
Reserved
These bits are always read as 0. The write value should
always be 0.
Transmit End Interrupt Enable
When this bit is set to 1, an SSTXI interrupt request
caused by transmit end is enabled.
R
5
0
-
Section 16 Synchronous Serial Communication Unit (SSU)
R
4
0
-
TEIE
R/W
3
0
Rev. 3.00 Sep. 28, 2009 Page 799 of 1650
R/W
TIE
2
0
R/W
RIE
1
0
CEIE
R/W
0
0
REJ09B0313-0300
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