DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 922

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 18 Serial Sound Interface (SSI)
Note:
Rev. 3.00 Sep. 28, 2009 Page 890 of 1650
REJ09B0313-0300
Bit
1
0
* The bit can be read or written to. Writing 0 initializes the bit, but writing 1 is ignored.
Bit Name
SWNO
IDST
Initial
Value
1
1
R/W
R
R
Description
System Word Number
This status bit indicates the current word number.
•
•
Idle Mode Status Flag
This status flag indicates that the serial bus activity has
stopped.
This bit is cleared if EN = 1 and the serial bus are
currently active.
This bit is automatically set to 1 under the following
conditions.
•
•
•
Note: If the external master stops the serial bus clock
TRMD = 0 (Receive mode)
SWNO indicates which system word the data in
SSIRDR currently represents. This value will
change as the data in SSIRDR is updated from the
shift register, regardless of whether SSIRDR has
been read.
TRMD = 1 (Transmit mode)
SWNO indicates which system word is required to
be written to SSITDR. This value will change as the
data is copied to the shift register, regardless of
whether the data is written to SSITDR.
SSI = Master transmitter (SWSD = 1 and
TRMD = 1)
This bit is set to 1 if the EN bit is cleared and the
data written to SSITDR has been completely output
from the serial data input/output pin (SSIDATA)
(that is, output of the system word is completed).
SSI = Master receiver (SWSD = 1 and TRMD = 0)
This bit is set to 1 if the EN bit is cleared and the
current system word is completed.
SSI = Slave transmitter/receiver (SWSD = 0)
This bit is set to 1 if the EN bit is cleared and the
current system word is completed.
before the current system word is completed,
this bit is not set.