DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 567
DS72030W200FPV
Manufacturer Part Number
DS72030W200FPV
Description
MPU, 32BIT, SH7203, ROMLESS, 240QFP
Manufacturer
Renesas Electronics America
Series
SH7200r
Datasheet
1.R5S72030W200FP.pdf
(1686 pages)
Specifications of DS72030W200FPV
Core Size
32bit
Program Memory Size
32KB
Cpu Speed
200MHz
Digital Ic Case Style
QFP
No. Of Pins
240
Supply Voltage Range
1.1V To 1.3V
Operating Temperature Range
-20°C To +85°C
Svhc
No SVHC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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11.4.4
In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit
counter.
This function works by counting the channel 1 counter clock upon overflow/underflow of
TCNT_2 as set in bits TPSC0 to TPSC2 in TCR.
Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode.
Table 11.42 shows the register combinations used in cascaded operation.
Note: When phase counting mode is set for channel 1, the counter clock setting is invalid and the
Table 11.42 Cascaded Combinations
For simultaneous input capture of TCNT_1 and TCNT_2 during cascaded operation, additional
input capture input pins can be specified by the input capture control register (TICCR). For input
capture in cascade connection, refer to section 11.7.22, Simultaneous Capture of TCNT_1 and
TCNT_2 in Cascade Connection.
Combination
Channels 1 and 2
Figure 11.19 Example of Buffer Operation When TCNT_0 Clearing is Selected for
TGRC_0
TGRB_0
TGRA_0
TGRA_0
counters operates independently in phase counting mode.
H'0000
TIOCA
TCNT_0 value
Cascaded Operation
H'0200
H'0200
H'0200
Upper 16 Bits
TCNT_1
TGRC_0 to TGRA_0 Transfer Timing
H'0450
H'0450
Transfer
H'0450
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Rev. 3.00 Sep. 28, 2009 Page 535 of 1650
Lower 16 Bits
TCNT_2
H'0520
H'0520
REJ09B0313-0300
H'0520
Time
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