DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 567

Manufacturer Part Number

DS72030W200FPV

MPU, 32BIT, SH7203, ROMLESS, 240QFP

Manufacturer

Renesas Electronics America

Program Memory Size

Digital Ic Case Style

Supply Voltage Range

1.1V To 1.3V

Operating Temperature Range

-20Â°C To +85Â°C

Rohs Compliant

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit

This function works by counting the channel 1 counter clock upon overflow/underflow of

TCNT_2 as set in bits TPSC0 to TPSC2 in TCR.

Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode.

Table 11.42 shows the register combinations used in cascaded operation.

Note: When phase counting mode is set for channel 1, the counter clock setting is invalid and the

Table 11.42 Cascaded Combinations

For simultaneous input capture of TCNT_1 and TCNT_2 during cascaded operation, additional

input capture input pins can be specified by the input capture control register (TICCR). For input

capture in cascade connection, refer to section 11.7.22, Simultaneous Capture of TCNT_1 and

TCNT_2 in Cascade Connection.

Channels 1 and 2

Figure 11.19 Example of Buffer Operation When TCNT_0 Clearing is Selected for

counters operates independently in phase counting mode.

TCNT_0 value

Cascaded Operation

Upper 16 Bits

TGRC_0 to TGRA_0 Transfer Timing

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)

Rev. 3.00 Sep. 28, 2009 Page 535 of 1650

Lower 16 Bits

REJ09B0313-0300