DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 776

no-image

DS72030W200FPV

Manufacturer Part Number
DS72030W200FPV
Description
MPU, 32BIT, SH7203, ROMLESS, 240QFP
Manufacturer
Renesas Electronics America
Series
SH7200r
Datasheet

Specifications of DS72030W200FPV

Core Size
32bit
Program Memory Size
32KB
Cpu Speed
200MHz
Digital Ic Case Style
QFP
No. Of Pins
240
Supply Voltage Range
1.1V To 1.3V
Operating Temperature Range
-20°C To +85°C
Svhc
No SVHC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Section 15 Serial Communication Interface with FIFO (SCIF)
15.3.8
SCBRR is an 8-bit register that is used with the CKS1 and CKS0 bits in the serial mode register
(SCSMR) and the BGDM and ABCS bits in the serial extension mode register (SCEMR) to
determine the serial transmit/receive bit rate.
The CPU can always read and write to SCBRR. SCBRR is initialized to H'FF by a power-on reset.
Each channel has independent baud rate generator control, so different values can be set in three
channels.
The SCBRR setting is calculated as follows:
• Asynchronous mode:
Rev. 3.00 Sep. 28, 2009 Page 744 of 1650
REJ09B0313-0300
When baud rate generator operates in normal mode (when the BGDM bit of SCEMR is 0):
When baud rate generator operates in double speed mode (when the BGDM bit of
SCEMR is 1):
Bit Rate Register (SCBRR)
N =
N =
N =
N =
64 × 2
32 × 2
32 × 2
16 × 2
Initial value:
2n-1
2n-1
2n-1
2n-1
× B
× B
× B
× B
R/W:
Bit:
× 10
× 10
× 10
× 10
R/W
7
1
6
6
6
6
− 1 (Operation on a base clock with a frequency of 16 times
− 1 (Operation on a base clock with a frequency of 8 times
− 1 (Operation on a base clock with a frequency of 16 times
− 1 (Operation on a base clock with a frequency of 8 times
R/W
6
1
the bit rate)
the bit rate)
the bit rate)
the bit rate)
R/W
5
1
R/W
4
1
R/W
3
1
R/W
2
1
R/W
1
1
R/W
0
1

Related parts for DS72030W200FPV