DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 277

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Note:
9.3.2
In this LSI, the data bus width of area 0 and the initial data bus width of areas 1 to 7 can be set to
16, or 32 bits through external pins during a power-on reset. The bus width of area 0 cannot be
modified after a power-on reset. The initial data bus width of areas 1 to 7 is set to the same size as
that of area 0, but can be modified to 8, 16, or 32 bits through register settings during program
execution. Note that the selectable data bus widths may be limited depending on the connected
memory type.
After a power-on reset, the LSI starts execution of the program stored in the external memory
allocated in area 0. Since ROM is assumed as the external memory in area 0, minimum pin
functions such as the address bus, data bus, CS0, and RD are available. The sample access
waveforms shown in this section include other pins such as BS, RD/WR, and WEn, which are
available after they are selected through the pin function controller. Do not attempt any form of
memory access other than reading of area 0 until the pin function settings have been completed by
the program. When the LSI has been started up with a 32-bit bus and the bus width of an area
other than area 0 is changed to 16 bits, the A1 pin setting becomes necessary for access to that
area. In the same way, both A1 and A0 pin settings become necessary when the bus width of an
area is changed to 8 bits. When area 7 is in use, the CS7 and A0 functions are assigned to the same
pin. In this case, therefore, note that the 8-bit bus width is not selectable.
For details on pin function settings, see section 25, Pin Function Controller (PFC).
Table 9.3
Internal Address
H'80000000 to H'FFFBFFFF Other
H'FFFC0000 to H'FFFFFFFF Other
MD
1
0
* For the on-chip RAM space, access the addresses shown in section 27, On-Chip RAM.
Data Bus Width and Pin Function Setting in Each Area
For the on-chip peripheral module space, access the addresses shown in section 30,
List of Registers. Do not access addresses which are not described in these sections.
Otherwise, the correct operation cannot be guaranteed.
Correspondence between External Pin (MD) and Data Bus Width
Space Memory to be Connected
On-chip RAM, reserved area*
On-chip peripheral modules, reserved area*
Data Bus Width
32 bits
16 bits
Rev. 3.00 Sep. 28, 2009 Page 245 of 1650
Section 9 Bus State Controller (BSC)
Cache
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REJ09B0313-0300