DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 446
DS72030W200FPV
Manufacturer Part Number
DS72030W200FPV
Description
MPU, 32BIT, SH7203, ROMLESS, 240QFP
Manufacturer
Renesas Electronics America
Series
SH7200r
Datasheet
1.R5S72030W200FP.pdf
(1686 pages)
Specifications of DS72030W200FPV
Core Size
32bit
Program Memory Size
32KB
Cpu Speed
200MHz
Digital Ic Case Style
QFP
No. Of Pins
240
Supply Voltage Range
1.1V To 1.3V
Operating Temperature Range
-20°C To +85°C
Svhc
No SVHC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Section 10 Direct Memory Access Controller (DMAC)
10.3.8
The DMA operation register (DMAOR) is a 16-bit readable/writable register that specifies the
priority level of channels at the DMA transfer. This register also shows the DMA transfer status.
Initial value:
Rev. 3.00 Sep. 28, 2009 Page 414 of 1650
REJ09B0313-0300
Bit
15, 14
13, 12
11, 10
Note:
R/W:
Bit:
*
DMA Operation Register (DMAOR)
Only 0 can be written to clear the flag after 1 is read.
Bit Name
⎯
CMS[1:0]
⎯
15
R
0
-
14
R
0
-
R/W
13
0
CMS[1:0]
Initial
Value
All 0
00
All 0
R/W
12
0
11
R
0
-
R/W
R
R/W
R
10
R
0
-
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Cycle Steal Mode Select
These bits select either normal mode or intermittent
mode in cycle steal mode.
It is necessary that the bus modes of all channels be
set to cycle steal mode to make the intermittent mode
valid.
00: Normal mode
01: Setting prohibited
10: Intermittent mode 16
11: Intermittent mode 64
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W
9
0
PR[1:0]
Executes one DMA transfer for every 16 cycles of
Bφ clock.
Executes one DMA transfer for every 64 cycles of
Bφ clock.
R/W
8
0
R
7
0
-
R
6
0
-
R
5
0
-
R
4
0
-
R
3
0
-
R/(W)* R/(W)* R/W
AE
2
0
NMIF
1
0
DME
0
0
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