DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 883

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.3.10 NF2CYC Register (NF2CYC)
NF2CYC is an 8-bit readable/writable register that selects the range of the noise filtering for the
SCL and SDA pins. For details of the noise filter, see section 17.4.7, Noise Filter.
Bit
7 to 2
1
0
Bit Name
⎯
PRS
NF2CYC
Initial value:
Initial
Value
All 0
0
0
R/W:
Bit:
R
7
0
-
R/W
R
R/W
R/W
R
6
0
-
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Specifies the ratio of the high-level period to the low-
level period for the SCL signal. However, do not set
PRS to 1 when CKS[3:0] in ICCR1 is H'7 or H'F.
0: The ratio of high to low is 0.5 to 0.5.
1: The ratio of high to low is about 0.4 to 0.6.
0: The noise less than one cycle of the peripheral clock
1: The noise less than two cycles of the peripheral clock
Pulse Width Ratio Select
Noise Filtering Range Select
R
5
0
-
can be filtered out
can be filtered out
R
4
0
-
R
3
0
-
Rev. 3.00 Sep. 28, 2009 Page 851 of 1650
R
2
0
-
Section 17 I
PRS
R/W
1
0
R/W
CYC
NF2
0
0
2
C Bus Interface 3 (IIC3)
REJ09B0313-0300