DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 569

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DS72030W200FPV

Manufacturer Part Number
DS72030W200FPV
Description
MPU, 32BIT, SH7203, ROMLESS, 240QFP
Manufacturer
Renesas Electronics America
Series
SH7200r
Datasheet

Specifications of DS72030W200FPV

Core Size
32bit
Program Memory Size
32KB
Cpu Speed
200MHz
Digital Ic Case Style
QFP
No. Of Pins
240
Supply Voltage Range
1.1V To 1.3V
Operating Temperature Range
-20°C To +85°C
Svhc
No SVHC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
(3)
Figure 11.22 illustrates the operation when TCNT_1 and TCNT_2 have been cascaded and the
I2AE bit in TICCR has been set to 1 to include the TIOC2A pin in the TGRA_1 input capture
conditions. In this example, the IOA0 to IOA3 bits in TIOR_1 have selected the TIOC1A rising
edge for the input capture timing while the IOA0 to IOA3 bits in TIOR_2 have selected the
TIOC2A rising edge for the input capture timing.
Under these conditions, the rising edge of both TIOC1A and TIOC2A is used for the TGRA_1
input capture condition. For the TGRA_2 input capture condition, the TIOC2A rising edge is used.
TGRA_1
TGRA_2
TCNT_1
TIOC1A
TIOC2A
H'FFFF
H'C256
H'6128
H'0000
Cascaded Operation Example (b)
TCNT_2 value
TCLKC
TCLKD
TCNT_2
TCNT_1
FFFD
Figure 11.21 Cascaded Operation Example (a)
Figure 11.22 Cascaded Operation Example (b)
H'0512
0000
FFFE
As I1AE in TICCR is 0, data is not captured in TGRA_2 at the TIOC1A input timing.
FFFF
H'0512
0000
H'0513
0001
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
0001
0002
Rev. 3.00 Sep. 28, 2009 Page 537 of 1650
H'0514
H'C256
H'0513
0001
0000
FFFF
REJ09B0313-0300
0000
Time

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