IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 103
IPR-PCIE/8
Manufacturer Part Number
IPR-PCIE/8
Description
IP CORE Renewal Of IP-PCIE/8
Manufacturer
Altera
Type
MegaCorer
Specifications of IPR-PCIE/8
Software Application
IP CORE, Interface And Protocols, PCI
Supported Families
Arria GX, Cyclone II, HardCopy II, Stratix II
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Function
PCI Express Compiler, x8 Link Width
License
Renewal License
Lead Free Status / RoHS Status
na
Lead Free Status / RoHS Status
na
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Specifications
Altera Corporation
December 2006
Notes for
(1) where n is the virtual channel number; For x1 and x4, n can be 0 - 3
(2) For x8, n can be 0 or 1
Table 3–29. Data Phase Signals (Part 2 of 2)
Signal
Table 3–29
I/O
Transaction Examples Using Receive Signals
This section provides additional examples that illustrate how transaction
signals interact:
■
■
■
■
■
In each waveform, a strong horizontal line separates descriptor signals
from data signals.
Transaction without data payload
Retried transaction and masked non-posted transactions
Transaction aborted
Transaction with data payload
Transaction with data payload and wait states
PCI Express Compiler Version 6.1
Description
PCI Express Compiler User Guide
3–65
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