IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 45

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Specifications
Altera Corporation
December 2006
Receive Buffer Reordering
The receive data path implements a receive buffer reordering function
that allows posted and completion transactions to pass non-posted
transactions (as allowed by PCI Express ordering rules) when the
application layer is unable to accept additional non-posted transactions.
The application layer dynamically enables the Rx Buffer reordering by
asserting the rx_mask signal. rx_mask masks non-posted request
transactions made to the application interface so that only posted and
completion transactions are presented to the application.
The MegaCore function operates in receive buffer bypass mode when
rx_mask is asserted. However, if masked requests exist, the MegaCore
function exits receive buffer bypass mode upon deassertion of rx_mask.
Data Link Layer
The data link layer is located between the transaction layer and the
physical layer. It is responsible for maintaining packet integrity and for
communication (by data link layer packet transmission) at the PCI
Express link level (as opposed to component communication by
transaction layer packet transmission within the fabric). Specifically, the
data link layer is responsible for the following:
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Figure 3–3
Link management through the reception and transmission of data
link layer packets, which are used:
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Data integrity through generation and checking of CRCs for
transaction layer packets and data link layer packets
Transaction layer packet retransmission in case of NAK data link
layer packet reception using the retry buffer
Management of the retry buffer
Link retraining requests in case of error (through the LTSSM of the
physical layer)
PCI Express Compiler Version 6.1
To initialize and update flow control credits for each virtual
channel
For power management of data link layer packet reception and
transmission
To transmit and receive ACK/NACK packets
illustrates the architecture of the data link layer.
PCI Express Compiler User Guide
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