IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 204

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

BFM Procedures and Functions
5–54
PCI Express Compiler User Guide
Syntax
Argument
Return
Syntax
Argument
Table 5–37. ebfm_log_stop_sim Procedure
Table 5–38. ebfm_log_set_suppressed_msg_mask Procedure
VHDL:
Verilog VHDL:
success
Always 0
bfm_log_set_suppressed_msg_mask (msg_mask)
msg_mask
ebfm_log_stop_sim(success
ebfm_log_stop_sim VHDL Procedure or Verilog HDL Function
The ebfm_log_stop_sim procedure stops the simulation.
ebfm_log_set_suppressed_msg_mask Procedure
The ebfm_log_set_suppressed_msg_mask procedure controls
which message types are suppressed. This alters the Displayed by
Default settings described in
When set to a 1, this process stops the simulation with a message indicating
successful completion. The message is prefixed with SUCCESS:.
Otherwise, this process stops the simulation with a message indicating
unsuccessful completion. The message is prefixed with FAILURE:.
This value applies only to the Verilog HDL function.
return:=ebfm_log_stop_sim(success
PCI Express Compiler Version 6.1
In VHDL, this argument is a subtype of std_logic_vector,
EBFM_MSG_MASK
EBFM_MSG_ERROR_CONTINUE
In Verilog HDL, this argument is
reg [EBFM_MSG_ERROR_CONTINUE: EBFM_MSG_DEBUG]
In both languages, a 1 in a specific bit position of the
causes messages of the type corresponding to the bit position to be
suppressed.
.
Table 5–35 on page
)
This vector has a range from
downto
);
5–52.
EBFM_MSG_DEBUG
Altera Corporation
December 2006
msg_mask
.
.