IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 54

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Functional Description
3–16
PCI Express Compiler User Guide
required. If the application layer cannot drain received packets
immediately in all cases, it also may be necessary to offer additional
credits to cover this delay.
Setting the Desired performance for received requests to High on the
Buffer Setup page under the Parameter Settings tab in the MegaWizard
interface will configure the Rx Buffer with enough space to meet the
above required credits. You can adjust the Desired performance for
received request up or down from the High setting to tailor the Rx Buffer
size to your delays and required performance.
Throughput of Non-Posted Reads
To support a high throughput of read data, you must analyze the overall
delay from the application layer issuing the read request until all of the
completion data has been returned. The application must be able to issue
enough read requests, and the read completer must be capable of
processing (or at least offering enough non-posted header credits) to
cover this delay.
However, much of the delay encountered in this loop is well outside the
PCI Express MegaCore function and is very difficult to estimate. PCI
Express switches can be inserted in this loop, which makes determining a
bound on the delay more difficult.
However, maintaining maximum throughput of completion data packets
is important. PCI Express Endpoints must offer an infinite number of
completion credits. However, the PCI Express MegaCore function must
buffer this data in the Rx Buffer until the application can process it. The
difference is that the PCI Express MegaCore function is no longer
managing the Rx Buffer through the flow control mechanism. Instead, the
application is managing the Rx Buffer by the rate at which it issues read
requests.
To determine the appropriate settings for the amount of space to reserve
for completions in the Rx Buffer, you must make an assumption about
how long read completions take to be returned. This can be estimated in
terms of an additional delay above the FC Update Loop Delay as
discussed in the section
paths for the Read Requests and the Completions are not exactly the same
as those for the Posted Writes and FC Updates within the PCI Express
Logic. However, the delay differences are probably small compared with
the inaccuracy in guessing what the external Read to Completion delays
are.
PCI Express Compiler Version 6.1
“Throughput of Posted Writes” on page
Altera Corporation
December 2006
3–11. The