IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 171

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Testbench & Example Designs
Altera Corporation
December 2006
4.
5.
c.
d.
Finds a suitable BAR to access the example endpoint design control
register space. One of the BARs 2 or 3 must be at least a 128 byte
memory BAR to perform the DMA channel test. The
find_mem_bar procedure in the altpcietb_bfm_driver does this.
If a suitable BAR is found in the previous step, the example
endpoint design DMA channel is tested by the procedure
target_dma_test in the altpcietb_bfm_driver. This procedure
executes the following substeps:
a.
b.
c.
d.
PCI Express Compiler Version 6.1
Reads the same 4,096 bytes from the target memory to a
separate location in the BFM shared memory, which is done by
a call to the ebfm_barrd_wait procedure in
altpcietb_bfm_rdwr. This procedure blocks (waits) until the
completion has been received for the read.
The data read back from the target memory is checked to
ensure the data is the same as what was initially written, which
is done by a call to the shmem_chk_ok procedure in the
altpcietb_bfm_shmem.
Sets up a 4,096 byte data pattern in the BFM shared memory,
which is done by a call to the shemem_fill procedure in
altpcietb_bfm_shmem.
Sets up the DMA channel control registers and starts the DMA
channel to transfer data from BFM shared memory to the
master memory in the example design. This is done by a series
of calls to the ebfm_barwr_imm procedure in
altpcietb_bfm_rdwr. The last of these ebfm_barwr_imm calls
starts the DMA channel.
Waits for the DMA channel to finish by checking the DMA
channel in-progress bit in the control register space until it is
clear. This is done by a loop around the call to the
ebfm_barrd_wait procedure in altpcietb_bfm_rdwr.
Sets up the DMA channel control registers and starts the DMA
channel to transfer data back from the example design master
memory to the BFM shared memory. This is done by a series of
calls to the ebfm_barwr_imm procedure in
altpcietb_bfm_rdwr. The last of these ebfm_barwr_imm calls
starts the DMA channel.
PCI Express Compiler User Guide
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