IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 62

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Functional Description
3–24
PCI Express Compiler User Guide
Correctable
Uncorrectable, Non-Fatal Device Software
Uncorrectable, Fatal
Table 3–12. Error Classification
Type
Hardware
System Software
Responsible Agent
■
■
Some time adjustment may be necessary if one or more switches are
located between the endpoint and the root port.
1
Error Handling
Each PCI Express compliant device must implement a basic level of error
management and can optionally implement advanced error
management. The MegaCore function does both, as described in this
section. Given its position and role within the fabric, error handling for a
root port is more complex than that of an endpoint.
The PCI Express specifications defines three types of errors, outlined in
Table
For L0s, the opposite component and the exit latency of each
component between the root port and endpoint is compared with the
endpoint’s acceptable latency. For example, for an endpoint
connected to a root port, if the root port’s L0s exit latency is 1 µs and
the endpoint’s L0s acceptable latency is 512 ns, software will
probably not enable the entry to L0s for the endpoint.
For L1, software calculates the L1 exit latency of each link between
the endpoint and the root port, and compares the maximum value
with the endpoint’s acceptable latency. For example, for an endpoint
connected to a root port, if the root port’s L1 exit latency is 1.5 µs and
the endpoint’s L1 exit latency is 4 µs, and the endpoint acceptable
latency is 2 µs, the exact L1 exit latency of the link will be 4 µs and
software will probably not enable the entry to L1.
3–12.
PCI Express Compiler Version 6.1
To maximize performance, Altera recommends that you set L0s
and L1 acceptable latency values to their minimum values.
While correctable errors may affect system performance, data
integrity is maintained.
Uncorrectable nonfatal errors are defined as errors in which
data is lost, but system integrity is maintained, i.e., the fabric
may lose a particular TLP, but it still works without problems.
Errors generated by a loss of data and system failure are
considered uncorrectable and fatal. Software must determine
how to handle such errors: whether to reset the link or
implement other means to minimize the problem.
Description
Altera Corporation
December 2006