IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 51

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Specifications
Figure 3–5. Flow Control Update Loop
Altera Corporation
December 2006
Layer
App
1
Control
Check)
Gating
(Credit
Logic
Flow
Allow
Transaction
Layer
Data Source
Consumed
Counter
Credits
2
Credit
Limit
Incr
The following numbered steps describe each step in the Flow Control
Update loop. The corresponding numbers on the diagram above show
the general area to which they correspond.
1.
2.
3.
4.
7
Data Link
Update
Decode
DLLP
Layer
When the Application Layer has a packet to transmit, the number of
credits required is calculated. If the current value of the Credit Limit
minus Credits Consumed is greater than or equal to the required
credits, then the packet can be transmitted immediately. However, if
the Credit Limit minus Credits Consumed is less than the required
credits, then the packet must be held until the Credit Limit is raised
to a sufficient value by an FC Update DLLP. This check is performed
separately for both the header and data credits, a single packet only
consumes a single header credit.
After the packet is selected to transmit, the Credits Consumed
register is incremented by the number of credits consumed by this
packet. This happens for both the header and data Credit
Consumed registers.
The packet is received at the other end of the link and placed in the
Rx Buffer.
At some point the packet is read out of the Rx Buffer by the
Application Layer. After the entire packet is read out of the Rx
Buffer, the Credit Allocated register can be incremented by the
number of credits the packet has used. There are separate Credit
Allocated registers for the Header and Data credits.
FC
PCI Express Compiler Version 6.1
Data Packet
Physical
Layer
FC Update DLLP
Express
Link
PCI
Physical
Layer
6
Data Link
Generate
Update
Layer
DLLP
PCI Express Compiler User Guide
FC
5
Data Sink
3
Allocated
Transaction
Credit
Buffer
Layer
Rx
Incr
4
Data Packet
Layer
App
3–13