IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 112

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Signals
3–74
PCI Express Compiler User Guide
Figure 3–30. Stratix GX PHY, 100 MHz Reference Clock Configuration
Note to
(1)
If you want to use other outputs of the enhanced PLL for other purposes
or with different phases or frequencies, you should use the 125-MHz
reference clock mode and use a 100- to 125-MHz PLL external to the
MegaCore function.
Stratix GX PHY, 125 MHz Reference Clock
When implementing the Stratix GX PHY with a 125-MHz reference clock,
you must provide a 125-MHz clock on the refclk input. The same clock
is provided to the clk125_out signal with no delay.
You must connect clk125_out back to the clk125_in input, for
example, through a distribution circuit needed in the application. All of
the function’s interfaces, including the user application interface and the
PIPE interface, are synchronous to the clk125_in input. See
Figure
Clock Source
100-MHz
User and PIPE interface signals are synchronous to clk125_in.
PCI Express Compiler Version 6.1
3–31.
Figure
3–30:
refclk
clk125_in
altpcie_64b_x4_pipen1b: Stratix GX 100 MHz
PLL
100 -> 125
clk
ALTGXB Transceiver
inclk
rx_cruclk
tx_coreclk
MegaCore Function
Altera Corporation
All Logic in
December 2006
clk125_out
(1)