IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 123

IP CORE Renewal Of IP-PCIE/8

IPR-PCIE/8

Manufacturer Part Number
IPR-PCIE/8
Description
IP CORE Renewal Of IP-PCIE/8
Manufacturer
Altera
Type
MegaCorer
Datasheets

Specifications of IPR-PCIE/8

Software Application
IP CORE, Interface And Protocols, PCI
Supported Families
Arria GX, Cyclone II, HardCopy II, Stratix II
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Function
PCI Express Compiler, x8 Link Width
License
Renewal License
Lead Free Status / RoHS Status
na
Lead Free Status / RoHS Status
na
Specifications
Figure 3–39. Example Implementation of the MSI Handler Block
Altera Corporation
December 2006
Vector 0
Vector 1
app_int_sts0
app_int_sts1
R/W
R/W
There are 32 possible MSI messages. The number of messages requested
by a particular component does not necessarily correspond to the number
of messages allocated. For example, in
eight MSI but is only allocated two. In this case, the application layer
must be designed to use only two allocated messages.
Figure 3–40. MSI Request Example
app_int_en0
app_int_en1
8 Requested
2 Allocated
Endpoint
PCI Express Compiler Version 6.1
app_msi_req0
app_msi_req1
app_int_sts
Root Complex
Root
Port
Arbitration
Figure
MSI
Interrupt Register
PCI Express Compiler User Guide
Interrupt
msi_enable & Master Enable
Block
3–40, the endpoint requests
app_msi_req
app_msi_ack
CPU
3–85

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