IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 138

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

External PHY Support
Figure 4–3. 8-Bit DDR Mode
4–6
PCI Express Compiler User Guide
External connection in user logic
clk125_out
txdata
refclk
clk125_in
rxdata
8-bit DDR with a Source Synchronous TxClk
The implementation of the 8-bit DDR mode with a source synchronous
transmit clock (TxClk) is shown in Figure 4-4 and is included in the file
<variation name>.v or <variation name>.vhd and includes a PLL. The PLL
inclock is driven by refclk (pclk from the external PHY) and has the
following 3 outputs:
■
Mode 3
Q 1
Q 4
Edge Detect and Sync
A zero delay copy of the 125 MHz refclk used as the clk125_in
for the MegaCore function and also to clock DDR input registers for
the Rx data and status signals.
PLL
PCI Express Compiler Version 6.1
A
D
0
0
8-bit DDR without txclk
ENB
DDIO
ENB
0
0
0
A
D
Q 1
Q 4
clk250_early
Q 1
Q 4
ENB
D
A
out txclk
tlp_clk
Clk125_pll_in
PCIe IP MegaCore
txdata_h
txdata_l
refclk
clk125_in
Tlp_clkt
clk125_out
Altera Corporation
December 2006