IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 114

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Signals
3–76
PCI Express Compiler User Guide
Figure 3–32. Stratix GX PHY, 156.25 MHz Reference Clock Configuration
Note to
(1)
Stratix II GX PHY X1 & X4 100 MHz Reference Clock
When implementing the Stratix II GX PHY in a x1 or x4 configuration, the
100 MHz clock is connected directly to the ALT2GXB transceiver. The
clk125_out is driven by the output of the ALT2GXB transceiver.
The clk125_out must be connected back to the clk125_in input, possibly
through any distribution circuit needed in the specific application. All of
the interfaces of the function, including the user application interface and
the PIPE interface are synchronous to the clk125_in input. See
on page 3–78
Clock Source
156.25-MHz
User and PIPE interface signals are synchronous to clk125_in.
PCI Express Compiler Version 6.1
Figure
3–32:
for this clocking configuration.
refclk
clk125_in
altpcie_64b_x4_pipen1b: Stratix GX 156.25 MHz
inclk
rx_cruclk
tx_coreclk
ALTGXB Transceiver
coreclk_out
clk
MegaCore Function
All Logic in
Altera Corporation
December 2006
clk125_out
Figure 3–34
(1)