IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 84

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Signals
3–46
PCI Express Compiler User Guide
Notes for
(1) where n is the virtual channel number; For x1 and x4, n can be 0 - 3
(2) For x8, n can be 0 or 1
tx_reqn
tx_descn[127:0]
(1),
tx_ackn
(1),
Table 3–22. Standard Descriptor Phase Signals
(2)
(2)
Signal
Table 3–22
(1),
(2)
I
I
O
I/O
Transmit request. This signal must be asserted for each request. It is always
asserted with the
asserted. This signal does not need to be deasserted between back-to-back
descriptor packets.
Transmit descriptor bus. The transmit descriptor bus, bits 127:0 of a transaction,
can include a 3 or 4 DWORDS PCI Express transaction header. Bits have the same
meaning as a standard transaction layer packet header as defined by the PCI
Express Base Specification Revision 1.0a. Byte 0 of the header occupies bits
127:120 of the
on, with byte 15 in bits 7:0. See
Formats
The following bits have special significance:
●
●
●
●
●
Bit 126 of the descriptor indicates the type of transaction layer packet in transit:
●
●
The following list provides a few examples of bit placement on this bus:
●
●
●
Transmit acknowledge. This signal is asserted for one clock cycle when the
MegaCore function acknowledges the descriptor phase requested by the
application through the
descriptor can be requested for transmission through the
asserted) and the
Table 3–22
tx_desc[2]
tx_desc[2]
tx_data[31:0]
tx_desc[34]
tx_data[31:0]
tx_desc[2]
tx_data[63:32]
tx_desc[34]
tx_data[63:32]
tx_desc[126]
tx_desc[126]
tx_desc[105:96]: length[9:0]
tx_desc[126:125]: fmt[1:0]
tx_desc[126:120]: type[4:0]
PCI Express Compiler Version 6.1
for the header formats.
describes the standard descriptor phase signals.
tx_desc
tx_desc[127:0]
tx_desc
or
(64-bit address) set to 0: The first DWORD is located on
(64-bit address) set to 1: The first DWORD is located on bits
(32-bit address) set to 0: The first DWORD is located on bits
(32-bit address) set to 1: The first DWORD is located on bits
tx_desc[34]
set to 0: transaction layer packet without data
set to 1: transaction layer packet with data
.
.
.
.
tx_req
bus, byte 1 of the header occupies bits 119:112, and so
.
Appendix B, Transaction Layer Packet Header
signal. On the following clock cycle, a new
Description
indicate the alignment of data on
and must remain asserted until
tx_req
Altera Corporation
December 2006
signal (kept
tx_ack
tx_data
is
.