IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 253

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
December 2006
test_compliance
test_pwr
test_pcserror
test_rxerrtlp
Table C–3. test_in Signals (Part 2 of 5)
Signal
MAC ltssm 6:5
CFG
PMGT
PCS
DLL
Subblock
7
13:8
14
PCI Express Compiler Version 6.1
Bit
Compliance test mode. Disable/force compliance mode:
●
●
Disable low power state negotiation. When asserted, this signal
disables all low power state negotiation and entry. This mode can
be used when the attached PHY does not support the electrical
idle feature used in low-power link states. The MegaCore function
will not attempt to place the link in Tx L0s state or L1 state when
this bit is asserted. For Stratix GX PHY implementations, this bit is
forced to a 1 internal to the MegaCore function.
Lane error injection. Disable/force compliance mode. The first
three bits indicate the following modes:
●
●
●
●
●
●
●
●
The last three bits indicate the lane:
●
●
●
●
Force transaction layer packet LCRC error detection. When
asserted, this signal forces the MegaCore function to treat the next
received transaction layer packet as if it had an LCRC error. These
bits are reserved on the x8 MegaCore function.
bit 0 completely disables compliance mode.
bit 1 forces compliance mode.
test_pcserror[2:0]: 000: normal mode
test_pcserror[2:0]: 001: inject data error
test_pcserror[2:0]: 010: inject disparity
error
test_pcserror[2:0]: 011: inject different
data
test_pcserror[2:0]: 100: inject SDP instead
of END
test_pcserror[2:0]: 101: inject STP instead
of END
test_pcserror[2:0]: 110: inject END instead
of data
test_pcserror[2:0]: 111: inject EDB instead
of END
test_pcserror[5:3]: 000: on lane 0
test_pcserror[5:3]: 001: on lane 1
test_pcserror[5:3]: 010: on lane 2
test_pcserror[5:3]: 011: on lane 3
Description
PCI Express Compiler User Guide
C–23