IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 153

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Testbench & Example Designs
Testbench
Figure 5–1. Testbench Top-Level Module: <variation name>_testbench
Altera Corporation
December 2006
<variation name>_example_pipen1b
Testbench Top Level (<variation name>_testbench)
Endpoint Example Design
The MegaWizard interface provides the Testbench in the subdirectory
<variation name>_examples/simple_dma/testbench for the simple DMA
design example and <variation name>_examples/
chaining_dma/testbench for the chaining DMA design example in your
project directory. The testbench top level is named <variation
name>_testbench for the simple DMA example design, and <variation
name>_chaining_testbench for the chaining DMA example design.
This testbench allows the simulation of up to an eight-lane PCI Express
link using either the PIPE interfaces of the root port and endpoints or the
serial PCI Express interface. See
testbench.
The top-level of the testbench instantiates four main modules:
■
■
■
<variation name>_example_pipen1b —This is the example
endpoint design that includes your variation of the MegaCore
function. For more information about this module, see
Example Design” on page
altpcietb_bfm_rp_top_x8_pipen1b —This is the root port PCI
Express bus functional model (BFM). For detailed information about
this module, see
altpcietb_pipe_phy —There are eight instances of this module, one
per lane. These modules interconnect the PIPE MAC layer interfaces
of the root port and the endpoint. The module mimics the behavior
of the PIPE PHY layer to both MAC interfaces.
PCI Express Compiler Version 6.1
PIPE Interconnection
(altpcierd_pipe_phy)
Module (x8)
“Root Port BFM” on page
(altpcietb_bfm_driver_chaining)
Test Driver Module
Chaining DMA
5–5.
Figure 5–1
(altpcierd_bfm_rp_top_x8_pipen1b)
PCI Express Compiler User Guide
Root Port BFM
for a high level view of the
5–27.
(altpcietb_bfm_driver)
Test Driver Module
Simple DMA
“Simple DMA
5–3