IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 113

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Specifications
Altera Corporation
December 2006
Figure 3–31. Stratix GX PHY, 125 MHz Reference Clock Configuration
Note to
(1)
Stratix GX PHY, 156.25 MHz Reference Clock
When implementing the Stratix GX PHY with a 156.25-MHz reference
clock, you must provide a 156.25-MHz clock on the refclk input. The
156.25-MHz clock goes directly to the Stratix GX transceiver. The
transceiver’s coreclk_out output becomes the function’s 125-MHz
clk125_out output.
You must connect clk125_out back to the clk125_in input, for
example, through a distribution circuit needed in the application. All of
the function’s interfaces, including the user application interface and the
PIPE interface, are synchronous to the clk125_in input. See
Figure
User and PIPE interface signals are synchronous to clk125_in.
PCI Express Compiler Version 6.1
3–32.
Clock Source
Figure
125-MHz
3–31:
refclk
clk125_in
altpcie_64b_x4_pipen1b: Stratix GX 125 MHz
PCI Express Compiler User Guide
clk
ALTGXB Transceiver
inclk
rx_cruclk
tx_coreclk
MegaCore Function
All Logic in
clk125_out
(1)
3–75