IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 220

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Configuration Signals for x1 and x4 MegaCore Functions
A–4
PCI Express Compiler User Guide
k_bar[31:0]
k_bar[63:32]
k_bar[95:64]
k_bar[127:96]
k_bar[159:128]
k_bar[191:160]
k_bar[223:192]
k_cnt[95:0]
k_cnt[106:96]
k_cnt[111:107]
k_cnt[116:112]
k_cnt[119:117]
k_cnt[127:120]
k_vc0[7:0]
k_vc0[19:8]
k_vc0[27:20]
Table A–1. Configuration Signals for x1 and x4 MegaCore Functions (Part 4 of 6)
Signal
System: BAR Table
(BAR0)
System: BAR Table
(BAR1)
System: BAR Table
(BAR2)
System: BAR Table
(BAR3)
System: BAR Table
(BAR4)
System: BAR Table
(BAR5)
System: BAR Table (Exp
ROM)
Fixed to 0
Fixed to 17
Power Management: Idle
Threshold for L0s Entry
Fixed to 30
Fixed to 0
Fixed to 200
Calculated: VC Table
Posted Header Credit
Calculated: VC Table
Posted Data Credit
Calculated: VC Table Non-
Posted Header Credit
Value or Wizard
Page/Label
PCI Express Compiler Version 6.1
BAR0 size mask and read only fields (I/O space,
memory space, prefetchable). bit 31 - 4 = size mask, bit
3 = prefetchable, bit 2 = 64 bit, bit 1 = 0, bit 0 = I/O.
BAR1 size mask and read only fields (I/O space,
memory space, prefetchable). bit 31 - 4 = size mask, bit
3 = prefetchable, bit 2 = 64 bit, bit 1 = 0, bit 0 = I/O (or
bit 31 - 0 = size mask if previous 64 bit).
BAR2 size mask and read only fields (I/O space,
memory space, prefetchable). bit 31 - 4 = size mask, bit
3 = prefetchable, bit 2 = 64 bit, bit 1 = 0, bit 0 = I/O.
BAR3 size mask and read only fields (I/O space,
memory space, prefetchable). bit 31 - 4 = size mask, bit
3 = Prefetchable, bit 2 = 64 bit, bit 1 = 0, bit 0 = I/O (or
bit 31 - 0 = size mask if previous 64 bit).
BAR4 size mask and read only fields (I/O space,
memory space, prefetchable). bit 31 - 4 = size mask, bit
3 = prefetchable, bit 2 = 64 bit, bit 1 = 0, bit 0 = I/O.
BAR5 size mask and read only fields (I/O space,
memory space, prefetchable). bit 31 - 4 = size mask, bit
3 = prefetchable, bit 2 = 64 bit, bit1 = 0, bit 0 = I/O (or
bit 31 - 0 = size mask if previous 64 bit).
Expansion ROM BAR size mask. bit 31 - 11 = size
mask, bit 10 - 1 = 0, bit 0 = enable.
Reserved.
Flow control initialization timer (number in μs). Number
in cycles.
Idle threshold for L0s entry (in 256 ns steps).
Update flow control credit timer (number in μs).
Reserved.
Flow control Time-Out check (number in μs).
Receive flow control credit for VC0 posted headers.
Receive flow control credit for VC0 posted data.
Receive flow control credit for VC0 non-posted
headers.
Description
Altera Corporation
December 2006