IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 86

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Signals
3–48
PCI Express Compiler User Guide
Notes for
(1) where n is the virtual channel number; For x1 and x4, n can be 0 - 3
(2) For x8, n can be 0 or 1
tx_datan[63:0]
(1),
Table 3–23. Standard Data Phase Signals (Part 2 of 2)
(2)
Signal
Table 3–23
I
I/O
Table 3–24
Transmit data bus. This signal transfers data from the application interface to the
link. It is 2 DWORDS wide and is naturally aligned with the address in one of two
ways, depending on bit 2 of the transaction layer packet address, which is located
on bit 2 or 34 of the
layer packet header bit 125 of the
●
●
●
●
This natural alignment allows you to connect the
64-bit data path aligned on a QWORD address (in the little endian convention).
Bit 2 is set to 1 (5 DWORDS transaction).
Bit 2 is set to 0 (5 DWORDS transaction).
tx_data[63:32]
tx_data[63:32]
tx_data[31:0]
tx_data[31:0]
tx_desc[2]
tx_data[31:0]
tx_desc[34]
tx_data[31:0]
tx_desc[2]
tx_data[63:32]
tx_desc[34]
tx_data[63:32]
PCI Express Compiler Version 6.1
describes the advanced data phase signals.
1
1
X
X
X
X
(64-bit address) set to 1: The first DWORD is located on bits
2
2
(64-bit address) set to 0: The first DWORD is located on
(32-bit address) set to 0: The first DWORD is located on bits
(32-bit address) set to 1: The first DWORD is located on bits
tx_desc
.
.
Clock Cycles
Clock Cycles
3
3
.
.
DW 0
DW 0
DW 1
4
4
DW 3
DW 2
DW 2
DW 1
(depending on the 3 or 4 DWORDS transaction
5
5
DW 4
DW 3
DW 4
tx_desc
Description
6
6
X
X
X
X
signal).
tx_data[63:0]
Altera Corporation
December 2006
directly to a