IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 95

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Specifications
Figure 3–19. Inserting Wait States because of 4-DWORD Header Waveform
Altera Corporation
December 2006
Descriptor
Signals
Signals
Data
tx_desc[127:0]
tx_data[63:32]
tx_data[31:0]
tx_ack
tx_req
tx_ws
tx_err
tx_dfr
tx_dv
Transaction Layer Inserts Wait States because of 4-DWORD Header
In this example, the application transmits a 64-bit memory write
transaction. Address bit 2 is set to 1. See
inserted during the first two data phases because the MegaCore function
implements a small buffer to give maximum performance during
transmission of back-to-back transaction layer packets.
In clock cycle 3, the MegaCore function inserts a wait state because the
memory write 64-bit transaction layer packet request has a 4-DWORD
header. In this case,
1
X
X
PCI Express Compiler Version 6.1
2
MEMWR64
3
DW0
4
5
tx_dv
DW2
DW1
6
DW3
DW4
Clock Cycles
could have been sent one clock cycle later.
7
DW6
DW5
8
DW7
9
10
PCI Express Compiler User Guide
Figure
11
3–19. No wait states are
12
X
X
13
14
15
3–57