IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 117

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Specifications
Altera Corporation
December 2006
clk250_in
clk250_out
rstn
npor
srst
crst
app_clk
l2_exit
hotrst_exit
dlup_exit
Table 3–31. Global Signals (Part 2 of 2)
Signal
I
O
I
I
I
I
O
O
O
O
I/O
Input clock for the x8 MegaCore function. All of the MegaCore function I/O signals (except
refclk
must be identical in frequency to the
the x8 MegaCore Function.
Output from the x8 MegaCore function. 250-MHz clock output derived from the
input. This signal is only on the x8 MegaCore Function.
Asynchronous Reset of Configuration Space and Data Path Logic. Active Low. This
signal is only available on the x8 MegaCore function.
Power on reset. This signal is the asynchronous active-low power-on reset signal. This
reset signal is used to initialize all configuration space sticky registers, PLL, and SERDES
circuitry. In 100- or 156.25-MHz reference clock implementations,
low while
Synchronous data path reset. This signal is the synchronous reset of the data path state
machines of the MegaCore function. It is active high. This signal is only available on the
x1 and x4 MegaCore functions.
Synchronous configuration reset. This signal is the synchronous reset of the nonsticky
configuration space registers of the MegaCore function. It is active high. This signal is
only available on the x1 and x4 MegaCore functions.
Output clock from x1 MegaCore function to the application layer. The clock can be
125Mhz or 62.5Mhz and is derived from
function.
L2 exit. The PCI Express specifications define fundamental hot, warm, and cold reset
states. A cold reset (assertion of
exits L2 state (signaled by assertion of this signal). This signal is active low and otherwise
remains high.
Hot reset exit. This signal is asserted for 1 clock cycle when the LTSSM exists hot reset
state. It informs the application layer that it is necessary to assert a global reset (
and
DL up exit. This signal indicates the transition from DL_UP to DL_DOWN. It is another
source of internal reset and should cause the assertion of the
synchronous resets. This signal is active low.
srst
Figure 3–35
,
npor
clk250_out
). This signal is active low and otherwise remains high.
PCI Express Compiler Version 6.1
is asserted.
shows the function’s global reset signals.
, and
npor
crst
) are synchronous to this clock signal. This signal
clk250_out
Description
and
refclk
srst
. This signal is only on the x1Megacore
) must be performed when the LTSSM
PCI Express Compiler User Guide
clock signal. This signal is only on
crst
clk125_out
and
srst
refclk
crst
is held
3–79