IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 89

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Specifications
Altera Corporation
December 2006
tx_cred[39:28]
tx_cred[47:40]
tx_cred[59:48]
tx_cred[60]
tx_cred[61]
tx_cred[62]
tx_cred[63]
tx_cred[64]
tx_cred[65]
Table 3–26. tx_cred[65:0] bits for x8 MegaCore Function (Part 2 of 2)
Bit
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
0: No credits available
1: Sufficient credit available for at least 1
TLP
0: No credits available
1: Sufficient credit available for at least 1
TLP
0: Posted Header Credits are not infinite
1: Posted Header Credits are infinite
0: Posted Data Credits are not infinite
1: Posted Data Credits are infinite
0: Non-Posted Header Credits are not
infinite
1: Non-Posted Header Credits are infinite
0: Non-Posted Data Credits are not
infinite
1: Non-Posted Data Credits are infinite
0: Completion Credits are not infinite
1: Completion Credits are infinite
0: Completion Data Credits are not infinite
1: Completion Data Credits are infinite
0: No credits available
1-256: number of credits available
257-511: reserved
Transaction Examples Using Transmit Signals
This section provides examples that illustrate how transaction signals
interact:
■
■
■
■
■
■
■
■
In each waveform, a strong horizontal line separates descriptor signals
from data signals.
Ideal case transmission
Transaction layer not ready to accept packet
Possible wait state insertion
Priority given elsewhere
Transmit request can remain asserted between transaction layer
packets
Transaction layer inserts wait states because of 4-DWORD header
Multiple wait states throttle transmission of data
Error asserted and transmission is nullified
PCI Express Compiler Version 6.1
Value
Non-Posted Data
Ignore this field if value of the Non-Posted
Data credits,
Completion Header
Completion Data: Posted Data: 9 bits
permit advertisement of 256 credits,
which corresponds to 4KB, the Maximum
Payload Size.
Posted Header credits are infinite when
set to 1.
Posted Data credits are infinite.when set
to 1.
Non-Posted Header credits are infinite
when set to 1.
Non-Posted Data credits are infinite when
set to 1.
Completion Header credits are infinite
when set to 1.
Completion Data credits are infinite when
set to 1.
PCI Express Compiler User Guide
tx_cred[63]
Description
,
set to 1.
3–51