IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 163

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Testbench & Example Designs
Figure 5–3. Top-Level Chaining DMA Example for Simulation
Altera Corporation
December 2006
Avalon-MM
buses
Chaining DMA Example
Header Register
DMA Write
Requester
Descriptor
Endpoint Memory
RC Slave
M
S
Header Register
M
DMA Read
S
Requester
Descriptor
The example endpoint design application layer has these features:
■
■
You can use the example endpoint design in the testbench simulation and
compile a complete design for an Altera device. All of the modules
necessary to implement the example design with the variation file are
contained in one of the following files, based on the language you use:
<variation name>_examples/chaining_dma/
<variation name>_example_chaining.vhd
or
<variation name>_examples/chaining_dma/
<variation name>_example_chaining.v
This file is created in the project directory when files are generated.
The following modules are included in the example design and located in
the subdirectory <variation name>_example/chaining_dma:
Shows you how to interface to the PCI Express MegaCore function
Provides a chaining DMA channel that can be used to initiate
memory read and write transactions on the PCI Express link
PCI Express Compiler Version 6.1
MegaCore Function
Variation (DUT)
PCI Express
Read
Descriptor
Table
Root Complex
PCI Express Compiler User Guide
Memory
Root Port
Data
CPU
Write
Descriptor
Table
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