IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 61

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Specifications
Altera Corporation
December 2006
Power State
L0s
L1
Table 3–11. L0s & L1 Exit Latency
L0s exit latency is calculated by the MegaCore function based on the number of fast training
sequences specified on the Power Management page of the MegaWizard interface and
maintained in a configuration space registry. Main power and the reference clock remain present
and the PHY should resynchronize quickly for receive data.
Resynchronization is performed through fast training order sets, which are sent by the opposite
component. A component knows how many sets to send because of the initialization process, at
which time the required number of sets are determined through TS1 and TS2.
L1 exit latency is specified on the Power Management page of the MegaWizard interface and
maintained in a configuration space registry. Both components across a link must transition to L1
low-power state together. When in L1, a component’s PHY is also in P1 low-power state for
additional power savings. Main power and the reference clock are still present, but the PHY can
shut down all PLLs to save additional power. However, shutting down PLLs causes a longer
transition time to L0.
L1 exit latency is higher than L0s exit latency. When the transmit PLL is locked, the LTSSM moves
to recovery, and back to L0 once both components have correctly negotiated the recovery state.
Thus, the exact L1 exit latency depends on the exit latency of each component (i.e., the higher
value of the two components). All calculations are performed by software; however, each
component reports its own L1 exit latency.
Each component must report in the configuration space if they use the
slot’s reference clock. Software then programs the common clock register,
depending on the reference clock of each component. Software also
retrains the link after changing the common clock register value to update
each exit latency.
component maintains two values for L0s and L1 exit latencies; one for the
common clock configuration and the other for the separated clock
configuration.
Acceptable Latency
The acceptable latency is defined as the maximum latency permitted for
a component to transition from a low power state to L0 without
compromising system performance. Acceptable latency values depend
on a component’s internal buffering, and are maintained in a
configuration space registry. Software compares the link exit latency with
the endpoint’s acceptable latency to determine whether the component is
permitted to use a particular power state.
trains on this same reference clock, the synchronization time of the
receive PLL is lower than if the reference clock is not the same for
both components.
PCI Express Compiler Version 6.1
Table 3–11
Description
describes the L0s and L1 exit latency. Each
PCI Express Compiler User Guide
3–23