IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 181

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Testbench & Example Designs
Altera Corporation
December 2006
3.
Assigns values to all the endpoint BAR registers. The BAR
addresses are assigned by the algorithm outlined below.
a.
b.
c.
d.
The above algorithm cannot always assign values to all BARs when
there are a few very large (1GB or greater) 32-bit BARs. Although
assigning addresses to all BARs may be possible, a more complex
algorithm would be required to effectively assign these addresses.
PCI Express Compiler Version 6.1
I/O BARs are assigned smallest to largest starting just above
the ending address of BFM shared memory in I/O space and
continuing as needed throughout a full 32-bit I/O space.
The 32-bit non-prefetchable memory BARs are assigned
smallest to largest, starting just above the ending address of
BFM shared memory in memory space and continuing as
needed throughout a full 32-bit memory space.
Assignment of the 32-bit prefetchable and 64-bit prefetchable
memory BARS are based on the value of the
addr_map_4GB_limit input to the ebfm_cfg_rp_ep. The
default value of the addr_map_4GB_limit is 0.
If the addr_map_4GB_limit input to the ebfm_cfg_rp_ep is
set to 0, then the 32-bit prefetchable memory BARs are assigned
largest to smallest, starting at the top of 32-bit memory space
and continuing as needed down to the ending address of the last
32-bit non-prefetchable BAR.
However, if the addr_map_4GB_limit input is set to 1, the
address map is limited to 4GB, the 32-bit and 64-bit prefetchable
memory BARs are assigned largest to smallest, starting at the
top of the 32-bit memory space and continuing as needed down
to the ending address of the last 32-bit non-prefetchable BAR.
If the addr_map_4GB_limit input to the ebfm_cfg_rp_ep
is set to 0, then the 64-bit prefetchable memory BARs are
assigned smallest to largest starting at the 4GB address
assigning memory ascending above the 4GB limit throughout
the full 64-bit memory space.
If the addr_map_4GB_limit input to the ebfm_cfg_rp_ep is
set to 1, then the 32-bit and the 64-bit prefetchable memory BARs
are assigned largest to smallest starting at the 4GB address and
assigning memory by descending below the 4GB address to
addresses memory as needed down to the ending address of the
last 32-bit non-prefetchable BAR.
PCI Express Compiler User Guide
5–31