IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 148

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

External PHY Constraint Support
External PHY
Constraint
Support
4–16
PCI Express Compiler User Guide
Stratix GX
Stratix II GX
TI XIO1100
Philips PX1011A
Custom
Table 4–4. External PHY Support Matrix
PHY Type
16-bit SDR
(pclk only)
-
-
-
-
x1, x4
Table 4–4
Type and Interface, the table lists the allowed lane widths.
The TI XIO1100 device has some additional control signals that need to be
driven by your design. These can be statically pulled high or low in the
board design, unless additional flexibility is needed by your design and
you want to drive them from the Altera device. These signals are:
■
■
■
PCI Express Compiler supports constraints. When you parameterize and
generate your MegaCore, Quartus II software creates a Tcl file that you
run when run compile your design. The Tcl files incorporates the
following constraints that you specify when you parameterize and
generate your MegaCore function:
■
■
■
■
1
-
x1, x4
16-bit SDR
(w/TxClk)
-
-
x1
P1_SLEEP must be pulled low. The PCI Express MegaCore function
requires the refclk (RX_CLK from the XIO1100) to remain active
while in the P1 powerdown state.
DDR_EN must be pulled high if your variation of the PCI Express
MegaCore function uses the 8-bit DDR (w/TxClk) mode. It must be
pulled low if the 16-bit SDR (w/TxClk) mode is used.
CLK_SEL must be set correctly based on the reference clock provided
to the XIO1100. Consult the XIO1100 data sheet for specific
recommendations.
pclk frequency constraint (125 MHz or 250 Mhz)
Setup and Hold constraints for the input signals
Clock to out constraints for the output signals
I/O Interface Standard
PCI Express Compiler Version 6.1
For more information on using the adding the constraint file
when you compile your design, refer to
on page
summarizes the PHY support matrix. For every supported PHY
8-bit DDR
(pclk only)
-
-
-
-
x1, x4
Allowed Interfaces and Lanes
2–15.
8-bit DDR
(w/TxClk)
-
-
x1
-
x1, x4
8-bit SDR
(pclk only)
-
-
-
-
x1, x4
8-bit SDR
(w/TxClk)
-
-
-
x1
x1, x4
“Compile the Design”
Altera Corporation
Serial
Interface
x1, x4
x1, x4, x8
-
-
-
December 2006