IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 245

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
December 2006
rx_8d00
rx_idl
rx_linkpad
rx_lanepad
rx_tsnum
lane_act
lane_rev
count0
count1
count2
count3
Reserved
Table C–1. test_out Signals for the x1 and x4 MegaCore Functions (Part 14 of 17)
Signal
MAC
ltssm
MAC
ltssm
MAC
ltssm
MAC
ltssm
MAC
ltssm
MAC
ltssm
MAC
ltssm
MAC
deskew
MAC
deskew
MAC
deskew
MAC
deskew
N/A
Subblock
375:368
383:376
391:384
399:392
407:400
411:408
415:412
418:416
421:419
424:422
427:425
439:428
PCI Express Compiler Version 6.1
Bit
Received 8 D0.0 symbol. This signal indicates that eight
consecutive idle data symbols have been received. This signal
is meaningful for config.idle and recovery.idle states.
The 4 MSB are always zero.
Received IDL OS. This signal indicates that an IDL OS has
been received on a per lane basis.
The 4 MSB are always zero.
Received link pad TS. This signal indicates that the link field of
the received TS1/TS2 is set to PAD for the specified lane.
The 4 MSB are always zero.
Received lane pad TS. This signal indicates that the lane field
of the received TS1/TS2 is set to PAD for the specified lane.
The 4 MSB are always zero.
Received consecutive identical TSNumber. This signal reports
the number of consecutive identical TS1/TS2 which have been
received with exactly the same parameters since entering this
state. When the maximum number is reached, this signal
restarts from zero.
This signal corresponds to the lane configured as logical lane 0
(may vary depending on lane reversal).
Lane active mode. This signal indicates the number of Lanes
that have been configured during training:
●
●
●
Reserved.
Deskew FIFO count lane 0. This signal indicates the number of
Words in the deskew FIFO for physical lane 0.
Deskew FIFO count lane 1. This signal indicates the number of
Words in the deskew FIFO for physical lane 1.
Deskew FIFO count lane 2. This signal indicates the number of
Words in the deskew FIFO for physical lane 2.
Deskew FIFO count lane 3. This signal indicates the number of
Words in the deskew FIFO for physical lane 3.
Reserved.
0001: 1
0010: 2
0100: 4
lane
lanes
lanes
Description
PCI Express Compiler User Guide
C–15