IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 223

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
December 2006
k_rxro
k_conf[15:0]
k_conf[31:16]
k_conf[39:32]
k_conf[63:40]
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Table A–2. Configuration Signals for x8 MegaCore Functions
Signal
Fixed to 1
Capabilities:
Vendor ID
Capabilities:
Device ID
Capabilities:
Revision ID
Capabilities:
Class Code
Capabilities:
Subsystem
Vendor ID
Capabilities:
Subsystem
Device ID
Fixed to 0b010
Fixed to 0
Fixed to 0
Fixed to 0
Fixed to 0
Fixed to 0
Fixed to 0
Fixed to 0
Fixed to 0
Fixed to 0
Fixed to 0
Fixed to 0
Fixed to 0
Value or Wizard
Page/Label
PCI Express Compiler Version 6.1
Receive Reordering: This signal implements reordering
capabilities on the Receive Path.
Vendor ID register.
Device ID register.
Revision ID register.
Class code register.
Subsystem vendor ID register.
Subsystem device ID register.
Power management capabilities register version field (set to 010).
Power management capabilities register PME clock field.
Reserved.
Power management capabilities register device-specific
initialization (DSI) field.
Power management capabilities register maximum auxiliary
current required while in d3cold to support PME.
Power management capabilities register D1 support bit.
Power management capabilities register D2 support bit.
Power management capabilities register PME message can be
sent in D0 state bit.
Power management capabilities register PME message can be
sent in D1 state bit.
Power management capabilities register PME message can be
sent in D2 state bit.
Power management capabilities register PME message can be
sent in D3 hot state bit.
Power management capabilities register PME message can be
sent in D3 cold state bit.
Reserved.
0: no Receive reordering
1: Receive reordering
Description
PCI Express Compiler User Guide
A–7