IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 85

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Specifications
Altera Corporation
December 2006
tx_dfrn
(1),
tx_dvn
(1),
tx_wsn
(1),
Table 3–23. Standard Data Phase Signals (Part 1 of 2)
(2)
(2)
(2)
Signal
I
I
O
I/O
Table 3–23
Transmit data phase framing. This signal is asserted on the same clock cycle as
tx_req
must be kept asserted until the clock cycle preceding the last data phase.
Transmit data valid. This signal is asserted by the user application interface to
signify that the
the clock cycle following assertion of
transmission. The MegaCore function will accept data only when this signal is
asserted and as long as
The application interface can rely on the fact that the first data phase will never
occur before a descriptor phase is acknowledged (through assertion of
However, the first data phase can coincide with assertion of
transaction layer packet header is only 3 DWORDS.
Transmit wait states. This signal is used by the MegaCore function to insert wait
states to prevent data loss. This signal might be used in the following
circumstances:
●
●
If the MegaCore function is not ready to acknowledge a descriptor phase (through
assertion of
transmission.When
To give a DLLP transmission priority.
To give a high-priority virtual channel or the retry buffer transmission priority
when the link is initialized with fewer lanes than are permitted by the link.
PCI Express Compiler Version 6.1
to request a data phase (assuming a data phase is needed). This signal
describes the standard data phase signals.
tx_ack
tx_data[63:0]
tx_dv
), it will automatically assert
tx_ws
is not asserted,
is not asserted.
signal is valid. This signal must be asserted on
Description
tx_dfr
tx_ws
PCI Express Compiler User Guide
until the last data phase of
tx_ws
should be ignored.
to throttle
tx_ack
if the
tx_ack
3–47
).