IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 48

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Functional Description
Figure 3–4. Physical Layer
3–10
PCI Express Compiler User Guide
Rx Packets
Tx Packets
Towards Data Link Layer
Generation
SKIP
Control & Status
Lane n
Lane 0
Lane n
Lane 0
Descrambler
Descrambler
Scrambler
Scrambler
Physical Layer
The physical layer is located at the lowest level of the MegaCore function,
i.e., it is the layer closest to the link. It encodes and transmits packets
across a link and accepts and decodes received packets. The physical
layer connects to the link through a high-speed SERDES running at
2.5 Gbps. The physical layer is responsible for the following actions:
■
■
■
Physical Layer Architecture
Figure 3–4
MAC Layer
State Machine
Initializing the link
Scrambling/descrambling and 8b/10b encoding/decoding of 2.5
Gbps per lane
Serializing and deserializing data
LTSSM
PCI Express Compiler Version 6.1
illustrates the physical layer architecture.
Rx MAC
Rx MAC
Lane
Lane
Interface
PIPE
Emulation Logic
Encoder
Encoder
Decoder
Decoder
8B/10B
8B/10B
8B/10B
8B/10B
PIPE
PHY layer
Elastic
Elastic
Buffer
Buffer
Altera Corporation
Rx+ / Rx-
Rx+ / Rx-
Tx+ / Tx-
Tx+ / Tx-
December 2006
Towards Link
Transmit
Data Path
Receive
Data Path