IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 142

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

External PHY Support
Figure 4–6. 8-bit SDR Mode with Source Synchronous Transmit Clock
4–10
PCI Express Compiler User Guide
refclk (250 Mhz)
rxdata
External connection in user logic
txdata
clk125_out
txclk
Mode 4
PLL
250Mhz SDR Mode with txclk
Q 1
Q 4
■
An edge detect circuit is used to detect the relationships between the 125
MHz clock and the 250 MHz rising edge to properly sequence the 16-bit
data into the 8-bit output register.
Edge Detect and Sync
clk250_early
A
D
0
0
ENB
An optional 62.5 MHz TLP Slow clock is provided for x1
implementations.
ENB
0
PCI Express Compiler Version 6.1
0
0
D
A
Q
Q
1
4
Q 1
Q 4
A
D
A
D
ENB
ENB
ENB
D
A
Q 1
Q 4
Q
Q
1
4
clk125_zero
tlp_clk
A
D
A
D
ENB
ENB
txdata_h
txdata_l
Q 1
Q 4
Q 1
Q 4
PCIe IP MegaCore
rxdata_h
clk125_in
tlp_clk
refclk
rxdata_l
Altera Corporation
December 2006