IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 60

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Functional Description
3–22
PCI Express Compiler User Guide
Active State Power Management (ASPM)
The PCI Express protocol mandates link power conservation, even if a
device has not been placed in a low power state by software. ASPM is
initiated by software but is subsequently handled by hardware. The
MegaCore function automatically shifts to one of two low power states to
conserve power:
■
1
■
1
Exit from L0s or L1
How quickly a component awakens from a low-power state, and even
whether a component has the right to transition to a low power state in
the first place, depends on exit latency and acceptable latency.
Exit Latency
A component’s exit latency is defined as the time it takes for the
component to awake from a low-power state to L0, and depends on the
SERDES PLL synchronization time and the common clock configuration
programmed by software. A SERDES generally has one transmit PLL for
all lanes and one receive PLL per lane.
■
■
L0s ASPM—The PCI Express protocol specifies the automatic
transition to L0s. In this state, the MegaCore function passes to
transmit electrical idle but can maintain an active reception interface
(i.e., only one component across a link moves to a lower power state).
Main power and reference clocks are maintained.
L1 ASPM—Transition to L1 is optional and conserves even more
power than L0s. In this state, both sides of a link power down
together, i.e., neither side can send or receive without first
transitioning back to L0
Transmit PLL—When transmitting, the transmit PLL must be locked.
Receive PLL—Receive PLLs train on the reference clock. When a lane
exits electrical idle, each receive PLL synchronizes on the receive
data (clock data recovery operation). If receive data has been
generated on the reference clock of the slot, and if each receive PLL
PCI Express Compiler Version 6.1
L0s ASPM is not supported when using the Stratix GX internal
PHY. It can be optionally enabled when using the Stratix II GX
internal PHY. It is supported for other device families to the
extent allowed by the attached external PHY device.
L1 ASPM is not supported when using the Stratix GX or Stratix
II GX internal PHY. It is supported for other device families to
the extent allowed by the attached external PHY device.
Altera Corporation
December 2006