IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 235
IPR-PCIE/8
Manufacturer Part Number
IPR-PCIE/8
Description
IP CORE Renewal Of IP-PCIE/8
Manufacturer
Altera
Type
MegaCorer
Specifications of IPR-PCIE/8
Software Application
IP CORE, Interface And Protocols, PCI
Supported Families
Arria GX, Cyclone II, HardCopy II, Stratix II
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Function
PCI Express Compiler, x8 Link Width
License
Renewal License
Lead Free Status / RoHS Status
na
Lead Free Status / RoHS Status
na
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Altera Corporation
December 2006
err_dll
err_trn
r2c_ack
c2r_ack
rxbuf_busy
rxfc_updated
r2c_ack
c2r_ack
rxbuf_busy
rxfc_updated
Table C–1. test_out Signals for the x1 and x4 MegaCore Functions (Part 4 of 17)
Signal
CFG
errmgt
CFG
errmgt
TRN
rxvc0
TRN
rxvc1
Subblock
89:85
98:90
102:99
106:013
PCI Express Compiler Version 6.1
Bit
Data link layer error. Data link layer error:
●
●
●
●
●
TRN error. Transaction layer error:
●
●
●
●
●
●
●
●
●
Receive VC0 status. Reports different events related to VC0.
●
●
●
●
Receive VC1 status. Reports different events related to VC1:
●
●
●
●
bit 0: Transaction layer packet error
bit 1: Data link layerP error
bit 2: Replay timer error
bit 3: Replay counter rollover
bit 4: Data link layer protocol error
bit 0: Poisoned transaction layer packet
received
bit 1: ECRC check failed
bit 2: Unsupported request
bit 3: Completion timeout
bit 4: Completer abort
bit 5: Unexpected Completion
bit 6: Receiver overflow
bit 7: Flow control protocol error
bit 8: Malformed transaction layer packet
bit 0: Transaction layer packet sent to
the configuration space
bit 1: Transaction layer packet received
from configuration space
bit 2: Receive buffer not empty
bit 3: Receive flow control credits
updated
bit 0: transaction layer packet sent to
the configuration space
bit 1: transaction layer packet received
from configuration space
bit 2: Receive buffer not empty
bit 3: Receive flow control credits
updated
Description
PCI Express Compiler User Guide
C–5
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