IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 143

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

External PHYs
Altera Corporation
December 2006
pcie_rstn
phystatus_ext
powerdown_ext[1:0]
refclk
pipe_txclk
rxdata0_ext[15:0]
rxdatak0_ext[1:0]
rxelecidle0_ext
rxpolarity0_ext
rxstatus0_ext[1:0]
rxvalid0_ext
txcompl0_ext
txdata0_ext[15:0]
txdatak0_ext[1:0]
txelecidle0_ext
rxdata1_ext[15:0]
rxdatak1_ext[1:0]
rxelecidle1_ext
rxpolarity1_ext
Table 4–2. 16-bit PHY Interface Signals (Part 1 of 2)
Signal Name
I
I
I
I
O
I
I
Direction
I
O
O
I
O
I
I
O
O
O
I
O
16-bit PHY Interface Signals
The external I/O signals for the 16-bit PIPE Interface Modes are
summarized in
whether the PHY mode has a TxClk, some of the signals may not be
available as noted.
PCI Express Compiler Version 6.1
PCI Express Reset signal, active low.
PIPE Interface phystatus signal. PHY is signaling
completion of the requested operation
PIPE Interface powerdown signal, requests the
PHY to enter the specified power state.
Input clock connected to the PIPE Interface
signal from the PHY. 125 MHz clock used to clock
all of the status and data signals
Source synchronous transmit cock signal for
clocking Tx Data and Control signals going to the
PHY.
PIPE Interface Lane 0 Rx Data signals, carries
the parallel received data.
PIPE Interface Lane 0 Rx Data K-character flags. Always
PIPE Interface Lane 0 Rx Electrical Idle
Indication.
PIPE Interface Lane 0 Rx Polarity Inversion
Control
PIPE Interface Lane 0 Rx Status flags.
PIPE Interface Lane 0 Rx Valid indication
PIPE Interface Lane 0 Tx Compliance control
PIPE Interface Lane 0 Tx Data signals, carries
the parallel transmit data.
PIPE Interface Lane 0 Tx Data K-character flags. Always
PIPE Interface Lane 0 Tx Electrical Idle Control
PIPE Interface Lane 1 Rx Data signals, carries
the parallel received data.
PIPE Interface Lane 1 Rx Data K-character flags. Only in x4
PIPE Interface Lane 1 Rx Electrical Idle
Indication.
PIPE Interface Lane 1 Rx Polarity Inversion
Control
Table
4–2. Depending on the number of lanes selected and
Description
PCI Express Compiler User Guide
pclk
Always
Always
Always
Always
Only in modes that
have the TxClk
Always
Always
Always
Always
Always
Always
Always
Always
Only in x4
Only in x4
Only in x4
Availability
4–11