IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 116

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Signals
Figure 3–34. Stratix II GX PHY x8 100 MHz Reference Clock
3–78
PCI Express Compiler User Guide
refclk
clk125_in
clk125_out
Table 3–31. Global Signals (Part 1 of 2)
Signal
Clock Source
I
I
O
I/O
100-MHz
Reference clock for the MegaCore function. It must be the frequency specified on the
System Settings page accessible from the Parameter Settings tab in the MegaWizard
interface. This signal is only required for Stratix GX PHY implementations. For generic
PIPE implementations, this signal drives the
Input clock for the x1 and x4 MegaCore function. All of the MegaCore function I/O signals
(except
signal must be a 125-MHz clock signal. In Stratix GX PHY implementations, the
clk125_out
a 125-MHz reference clock, the reference clock can also drive this signal. In generic PIPE
implementations, the
clk125_in
Output clock for the x1 and x4 MegaCore function. 125-MHz clock output derived from
the
implementations, the
MegaCore function.
User and PIPE
interface signals
are synchronous
to clk250_in
refclk
Utility Signals
Refer to
MegaCore function signals.
Table 3–31
refclk
. This signal is not on the x8 MegaCore function.
input in Stratix GX PHY implementations. In generic PIPE PHY
PCI Express Compiler Version 6.1
signal can drive it, if desired. In Stratix GX PHY implementations that use
Figure 3–12 on page 3–44
refclk
clk250_in
,
altpcie_64b_x8_pipen1b: Stratix II GX
clk125_out
describes the function’s global signals.
pclk
refclk
supplied by the PIPE PHY device typically drives
pll_inclk
ALTGXB Transceiver
clk
input drives this signal. This signal is not on the x8
MegaCore Function
, and
All Logic in
Description
npor
coreclkout
) are synchronous to this clock signal. This
clk125_out
for a diagram of all PCI Express
signal directly.
clk250_out
Altera Corporation
December 2006