IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 70

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Parameter Settings
3–32
PCI Express Compiler User Guide
PHY type
PHY interface
Lanes
Port type
Xcvr ref_clk
PCI Express version
Table 3–17. System Settings Page Parameters (Part 1 of 2)
Parameter
Custom
Stratix GX
Stratix II GX
TI XIO1100
Philips PX1011A
Serial,
16-bit SDR,
16-bit SDR w/TxClk,
8-bit DDR,
8-bit DDR w/TxClk,
8-bit SDR,
8-bit SDR w/TxClk
x1, x4, x8
Native Endpoint, Legacy
Endpoint
100 MHz, 125 MHz,
156.25 MHz
1.0A or 1.1
Table 3–17
Value
PCI Express Compiler Version 6.1
describes the parameters you can set on this page.
Allows all PHY interfaces (except serial), allows x1 and
x4 lanes
Stratix GX uses the Stratix GX device family's built-in
altgxb transceiver. Selecting this PHY allows only a
serial PHY interface and restricts the Number of Lanes
to be x1 or x4.
Stratix II GX uses the Stratix II GX device family's built-in
alt2gxb transceiver. Selecting this PHY allows only serial
PHY interface and the Number of Lanes can be x1, x4,
or x8.
TI XIO1100 allows an 8 -bit DDR with a transmit clock
(txclk) or a 16-bit SDR with a transmit clock PHY
interface. Both of these restricts the Number of Lanes
to x1.
Philips PX1011A uses a PHY interface of 8-bit SDR with
a TxClk. This option restricts the number of lanes to x1.
This selects the specific type of external PHY interface
based on datapath width and clocking mode. See
Chapter 4, External PHYs
PHY modes.
Stratix II GX and Stratix GX are serial only PHY
interfaces, and they are the only available serial
interfaces.
Specifies the maximum number of lanes supported.
The x8 value is supported only for a Stratix II GX PHY.
Specifies the port type. Altera recommends Native
endpoint for all new designs. Select Legacy Endpoint
only when you require I/O transaction support for
compatibility. See
more information.
Specifies the frequency of the
when using the Stratix GX PHY. The Stratix GX PHY can
use either a 125- or 156.25-MHz clock directly. If you
select 100 MHz, the MegaCore function uses a Stratix
GX PLL to create a 125-MHz clock from the 100-MHz
input.
If you use a generic PIPE, the
A Stratix II GX PHY requires a 100 MHz clock.
Selects the PCI Express specification that the variation
will be compatible with
“Endpoint Types” on page 3–2
Description
for additional detail on specific
refclk
refclk
Altera Corporation
input clock signal
is not required.
December 2006
for