IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 182

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Root Port BFM
5–32
PCI Express Compiler User Guide
4.
5.
The ebfm_cfg_rp_ep procedure also sets up a bar_table data
structure in BFM shared memory that lists the sizes and assigned
addresses of all endpoint BARs. This area of BFM shared memory is
write-protected, which means any user write accesses to this area cause a
fatal simulation error. This data structure is then used by subsequent BFM
procedure calls to generate read and write requests to particular offsets
from a BAR.
The configuration routine does not configure any advanced PCI Express
capabilities such as Virtual Channel Capability or Advanced Error
Reporting capability.
Besides the ebfm_cfg_rp_ep procedure in altpcietb_bfm_configure,
routines to read and write endpoint configuration space registers directly
are available in the altpcietb_bfm_rdwr VHDL package or Verilog HDL
include file.
Issuing Read & Write Transactions to the Application Layer
Read and write transactions are issued to the endpoint application layer
by calling one of the ebfm_bar procedures in altpcietb_bfm_rdwr. The
procedures and functions listed below are available in the VHDL package
file altpcietb_bfm_rdwr.vhd or in the Verilog HDL include file
altpcietb_bfm_rdwr.v. The complete list of available procedures and
functions is:
■
■
However, such a configuration is unlikely to be useful in real
systems. If the procedure is unable to assign the BARs, it displays an
error message and stops the simulation.
Based on the above BAR assignments, the root port configuration
space address windows are assigned to encompass the valid BAR
address ranges.
The endpoint PCI Control Register is set to enable master
transactions, memory address decoding, and I/O address decoding.
ebfm_barwr —writes data from BFM shared memory to an offset
from a specific endpoint BAR. This procedure returns as soon as the
request has been passed to the VC interface module for transmission.
ebfm_barwr_imm —writes a maximum of four bytes of immediate
data (passed in a procedure call) to an offset from a specific endpoint
BAR. This procedure returns as soon as the request has been passed
to the VC interface module for transmission.
PCI Express Compiler Version 6.1
Altera Corporation
December 2006